HYS=DISABLE_, CLK_DIV=IOCONFILTRCLKDIV0_, OD=DISABLE_, INV=INPUT_NOT_INVERTED_, MODE=INACTIVE_NO_PULL_DO, S_MODE=BYPASS_INPUT_FILTER_
I/O configuration for pin PIO0_5/RESET
| RESERVED | Reserved. |
| MODE | Selects function mode (on-chip pull-up/pull-down resistor control). 0 (INACTIVE_NO_PULL_DO): Inactive (no pull-down/pull-up resistor enabled). 1 (PULL_DOWN_RESISTOR_E): Pull-down resistor enabled. 2 (PULL_UP_RESISTOR_ENA): Pull-up resistor enabled. 3 (REPEATER_MODE_): Repeater mode. |
| HYS | Hysteresis. 0 (DISABLE_): Disable. 1 (ENABLE_): Enable. |
| INV | Invert input 0 (INPUT_NOT_INVERTED_): Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0). 1 (INPUT_INVERTED_HIGH): Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). |
| RESERVED | Reserved. |
| OD | Open-drain mode. 0 (DISABLE_): Disable. 1 (OPEN_DRAIN_MODE_ENAB): Open-drain mode enabled. This is not a true open-drain mode. |
| S_MODE | Digital filter sample mode. 0 (BYPASS_INPUT_FILTER_): Bypass input filter. 1 (1_CLOCK_CYCLE_INPUT): 1 clock cycle. Input pulses shorter than one filter clock are rejected. 2 (2_CLOCK_CYCLES_INPU): 2 clock cycles. Input pulses shorter than two filter clocks are rejected. 3 (3_CLOCK_CYCLES_INPU): 3 clock cycles. Input pulses shorter than three filter clocks are rejected. |
| CLK_DIV | Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved. 0 (IOCONFILTRCLKDIV0_): IOCONFILTRCLKDIV0. 1 (IOCONFILTRCLKDIV1_): IOCONFILTRCLKDIV1. 2 (IOCONFILTRCLKDIV2_): IOCONFILTRCLKDIV2. 3 (IOCONFILTRCLKDIV3_): IOCONFILTRCLKDIV3. 4 (IOCONFILTRCLKDIV4_): IOCONFILTRCLKDIV4. 5 (IOCONFILTRCLKDIV5_): IOCONFILTRCLKDIV5. 6 (IOCONFILTRCLKDIV6_): IOCONFILTRCLKDIV6. |
| RESERVED | Reserved. |